Tuesday, 24 April 2012

Conversion of EDWinXP project to Xilinx Netlist

Conversion of EDWinXP project to Xilinx Netlist (for FPGA, PLD input)

Visionics develops the EDA software EDWinXP (a pioneer in PCB Design and SPICE Simulation) have multiple functionalities. A design engineer can use the computerized tools provided in EDWinXP to create an electronic circuit, design the PCB and fabricate PCB. Complete design information is stored in the integrated project database, simultaneously accessible by Schematic Diagram Editor, PCB Layout Editor, Fabrication Output Manager and Simulators. Front and back annotation of all design changes is fully automatic.

Xilinx is a company that designs, develops and markets programmable logic products including integrated circuits (ICs), software design tools, predefined system functions delivered as intellectual property (IP) cores, design services. Xilinx sells both FPGAs and CPLDs programmable logic devices for electronic equipment manufacturers in end markets

Here we describe the possibility of EDWinXP as a tool to convert/ export the contents to FPGA/ PLD readable form.
The VHDL code written in EDWinXP VHDL Editor can be converted to Xilinx compatible edn format. The file obtained as the output can be downloaded to the Xilinx supporting FPGA burning software like an ISE design suite or similar software.

The Virtex series of FPGAs have integrated features that include FIFO and ECC logic, DSP blocks, PCI-Express controllers, Ethernet MAC blocks, and high-speed transceivers. In addition to FPGA logic, the Virtex series includes embedded fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and microprocessor cores

The Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume; e.g. displays, set-top boxes, wireless routers and other applications

How to convert EDWinXP project to Xilinx Netlist

Select EDWinXP Main > System > VHDL Editor and write the required VHDL code in the work space.  Save the code. Then select Build > Create XILINX Output.

On selecting it, a window will be opened as shown below
Choose the appropriate Conversion format i.e the Xilinx series and click on Convert.
Click on Yes to generate the edn file
The above fig indicates the generated edn file. This can be used by the Xilinx software for downloading.

Exporting of a Project to edn format

This option exports the netlist of the current project to the XILINX format. Select this option from the list of Export and point to the location where the output file (*.edn) should lie. To export the contents, click on the Export button. If the check box for View output file active the file is displayed in EDWinXP Viewer.

Activate Insert I/O buffers if the selected vhdl module is the topmost module of the design, ie. its input and output ports will be connected directly to I/O pads in the final implementation.

Note: Setting this option when compiling lower-level modules, or when the synthesized netlist is referenced in a higher-level netlist such as the one generated from a top-level schematic, may result in errors during placement and routing of the design. The target FPGA place-and-route software is Alliance 2.1.

EDWinXP can output to the following Xilinx output formats
  1. Xilinx 3000 series
  2. Xilinx 4000E series
  3. Xilinx 4000X series
  4. Xilinx 5200 series
  5. Xilinx 9000 series
  6. Xilinx Spartan series
  7. Xilinx SpartanXL series
  8. Xilinx Spartan2 series
  9. Xilinx Virtex series
  10. Xilinx VirtexE series
  11. Xilinx Virtex2 series
Note: The target FPGA place-and-route software is Alliance 2.1

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