Thursday 1 October 2015

Visionics celebrating 32nd Anniversary


Visionics, a subsidiary of Norlinvest Ltd celebrates 32nd Anniversary in EDA industry. At this moment, we thank all our customers who supported us and wish to receive the support in future also. We are fortunate to have a diverse group of clients who always keep us engaged and push us to deliver what is needed.

The History of Visionics dates back to 1983,when we introduced the first EDA package - The CAD ABC,which gained a lot of prominence. Over the years, we have been continuously introducing new EDA packages like CAD 1000, Comp CAD and the EE Designer series and has won many international awards. EDWinXP (PCB Designing and SPICE-based software) is the main product of Visionics. With its Principal office at Stockholm, Sweden, the company also has development centres in Russia, Estonia, and Japan.

In our customer list we have companies like Volvo, Ericsson, Bofors, GE, FCC (Federal Communications Commission) – USA and Universities in Sweden, UK, USA, Malaysia, Columbia and several Engineering colleges in India.Our latest product EDWinXP 1.90 download version comes with all features of EDWinXP including EDSpice Simulator and Full Libraries.


Our Vision is to create the best PC-based EDA systems and attain high level of customer satisfaction.We hope to celebrate with each and every one of you this important milestone in our history. And we especially look forward to, and will work hard to achieve, another 32 years of success

Wednesday 9 September 2015

Parallel Routing in EDWinXP1.95 & EDWinNET 1.0 Standard


In EDWinXP 1.95, Parallel Routing is one of the enhanced feature in PCB Layout Editor. This will help to make PCB circuits easier than the other versions of EDWinXP. We have added the same feature in EDWinNET 1.0 Standard Version.
             This option can be selected from Auto menu in Layout Editor, select Parallel Routing option. It will enable the Parallel routing mode. Enable Connections – Route.Earlier for Parallel routing of traces depress the key combination Shift + E prior to selecting a starting pad of a traces set. This enables the mode for blocking several pins. Selecting the pins will enable parallel routing window where you can specify the routing space. Specify the spacing and click on Accept button.
           After arriving to final destination for the leading trace, it can be connected in normal fashion. When leading trace is connected, the next unconnected is taken as the leading and parallel routing continues until all in the bunch been connected or operation aborted by ESC. Read More

Thursday 30 July 2015

Wirebonding in EDWinNET

AsPacker is a tool that aids the designer integrate bare die or chips into their projects. AsPacker automates the process eliminating errors that can be made during hand editing a package layout.The Wire Bond Explorer allows the packaging engineer to parametrically design the fan out pattern for a die. This tool also has a 3D Viewer allowing the designer to see the design from all angles. Cross referencing between the netlist and die is also available. Outputs in clued DXF format as well as an enhanced LIQ formatthat is currently accepted by PADS & EDWinNET.
Wire bonding is the method of making interconnections between an integrated circuit (IC) or other semiconductor device and its packaging during semiconductor device fabrication.
EDWinNET can now fabricate multichip modules from AsPacker.
Library Editor



EDWinXP 1.95 Features


The current version, EDWinXP 1.95 unveils a countless set of features with more flexible and enhanced editors, PCB Wizard,Enhanced 3D Viewer and Improved 3D IDF Viewer using Open GL and a new set of Libraries. The Editors comprise of Schematic Editor, Simulators – Mixed Mode Simulator and SPICE based simulator EDSpice, PCB Layout Editor – Create the PCB Layout, Fabrication Manager – generate Manufacturing output files for Photoplotter, NC Drill etc, Thermal Analyzer – check for hotspots on the board, Electromagnetic Analyzer (with Signal Integrity and Field analyzer) – check for electromagnetic effects on the board. 3D Viewers and Editors, VHDL Editor with facility of automatic project creation from VHDL source and Converters (CUPL, JEDEC, XILINX), Microcontroller Simulation using 8051,AVR,PIC,Motorola Microcontrollers, 3D Library Editor, Model Generators from VHDL for Mixed Mode and EDSpice Simulators with facility of automatic creation of model/ library along with other features. Apart from the major attraction, completely integrated design concept with Automatic Front and Back Annotation and 28,000 + Library Components and Library Editor for library component creation. EDWinXP supports Reverse Engineering – complete reconstruction of project database using full set of artworks in Gerber ASCII format or complicated PCB Outline. Other modules are VHDL/Truth Table to diagram converter, 3D IDF file viewer, Filter Designer, ODB++ export and import and much more.




Monday 6 July 2015

Workshop on Microcontroller and Embedded Systems using 8051

Visionics India Pvt Ltd, Technopark Trivandrum offers workshop in " Microcontroller and EmbeddedSystems using 8051 " for B.Tech(ECE,EEE,EIE,AEI)/ Diploma/ M.Sc,B.Sc graduates.The workshops will expose participants to not just the theoretical aspects – from fundamental to advanced levels – but also equip them practically .

Workshop Contents
  • *Introduction to 8051 Microcontroller
    • Architecture
    • Instruction set
    • Application
  • *Practical Session
    • Simple Programs on 8051
    • Code writing in EDWinXP Mix mode Simulator 8051 MMI
    • Introduction to all programmable pins in the microcontroller
    • Introduction to different tabs in MMI
    • C Editor
    • Assembly Editor
    • Listing View
    • Hex Editor
    • Disassembler
    • Output File
    • Errors and Warnings
    • How to import and export a bin file
    • How to export a hex file..

ARDUINO Workshop


Visionics India Pvt Ltd, Technopark Trivandrum offers Arduino workshop for B.Tech(ECE,EEE,EIE,AEI)/ Diploma/ M.Sc,B.Sc graduates. This workshop will help students to learn from the basics of Arduino hardware and software.Arduino is a popular Open Source Embedded Development Board. Uses various sensors, actuators and an integrated environment for developing different types of projects. A perfect introduction to Embedded System for beginners. The Workshop will include Study of Arduino IDE with practical sessions.

Duration: 2 Days

Prerequisite: Basic of C programming

Venue: College Lab

Conducted by: Visionics India Pvt Ltd, A-2 Periyar, Technopark, Trivandrum

Request For Workshop : Universities/Students can request for a workshop by sending their needs to training@visionics.co.in
Day 1:Arduino 
  • Introduction to Microcontroller and Microprocessor
  • Atmega 328 and its circuit
  • Arduino board Layout
  • Getting started with Arduino IDE to write programs
  • LED Blinking(digital output)
  • Switch(digital input)
  • Serial output(print)
  • Serial input(read)
  • Potentiometer(analog read)
  • Fading(analog out)
  • Water tank automation
  • LDR
  • Automatic Street Light

Day 2:Arduino Peripherals and Project essentials

  • Computer controlled robot
  • Temperature Sensor
  • LCD
  • Temperature value display in LCD
  • Accelerometer(vehicle control)
  • Ultrasonic Sensor

EDWinNET 1.0 Standard Version Released !!!


EDWinNET 1.0 Standard version comes with all Standard features of EDWinXP. This is the conversion and movement of EDWinXP to a new platform, .NET. 

EDWinNET 1.0 Standard is an EDA Software Package for automated design of electronic products. This integrated tool covers all stages of electronic design process - Schematic Capture, PCB Layout Design, Generation of PCB Manufacturing and Testing. Complete design information is stored in the integrated project simultaneously accessible by Schematic Diagram Editor, PCB Layout Editor, Fabrication Output Manager . This simulator provides EDWinXP users with the facility to analyze and validate the functionality and behaviour of circuits captured in the form of schematic diagrams.Front and back annotation of all design changes is fully automatic.

Wirebonding in EDWinNET using AsPacker

AsPacker – Wire Bond Explorer
          
        AsPacker is a tool to explore and develop bare Die wirebond solutions for PCBs, MCMs, Hybrids and Packages. AsPacker is a tool that aids the designer integrate bare die or chips into their design. It is fully programmable and flexible with many options to explore while trying to achieve the best design possible for your needs. High pin-out die can be a nightmare to deal with unless you have a tool like AsPacker do the work for you.
         It is simple to use and easy to earn. Anybody wishing to take advantage of using bare die or chips in their designs will benefit by using Aspacker. It eliminates the guess work of hand editing by using design rules to drive the process. For advanced users it can be used in the design of Multi Chip Modules, Hybrids Circuits and Packages.
         By using AsPacker, the time from start to finish is greatly reduced while increasing the design integrity and reliability. All commands are recorded as they are executed and can be edited and played back at any time. This makes the design process and set-up repeatable, reliable and reusable. Interface with EDWin is done by using an industry standard LIQ file format.

Industry – proven algorithms

         Original code stream was developed to assist MCM design houses in the early 1990’s. Second generation algorithms licensed to Mentor’s PADs and Synopsy's Sager systems and are still in use today. Third generation represents a complete rewrite of the algorithms to allow for a better user interface and integration of multiple tools into a single tool. Fourth generation continued to simplify the design process focusing more on the layout engineer eliminating parts of the code that dealt with ASIC design and tailored to work with EDWin.The fanout algorithms have been rewritten again to increasing the accuracy and reliability of the design process through the use of scripting and an easy to understand command language.

Superior QOR (Quality of Results)

        Patent Pending algorithm yields superior wirebond results like:
  • Minimum total wirebond length.
  • Minimum wirebond angles.
        Algorithm places die bond pads into geographic groups based on distances between die bond pads and bonds out each group separately. Whereas other tools center the substrate pads at the geometric center of each side and evenly spread out the pads regardless of gaps between die bond pads. This
  • Can lead to longer wirebonds.
  • Can create excessive wirebond angles
         AsPacker iteratively looks at multiple solutions and interactions between groups to generate the best final solution.Total Maximum Iterations can be set (defaults to 100) and the tool will stop before the max iterations if the changes between iterations is less than a set parameter (defaults to .01 micron).

Die with bond pad gaps

Typical tool solution
AsPacker Solution

Typical tool solutionAsPacker Solution

Notice substrate pads centered creating needless wirebond angles and lengths
Notice AsPacker solution generates minimum wirebond angles and lengths.



Typical Design Flow

  • Set up work path where design data resides.
    • Open an LIQ file(short format) or pinlist file created from the from the manufacturer’s die datasheet.
    • Both of these files contain the Die size and thickness along with the CBPs (Component Bond Pad size and location information).
    • This starts the project and establishes the basic parameters which will be build on.
    • All the files required for the project should be placed in this project directory.
    • This also becomes the default directory for other loads, saves, imports and exports.

      • Add the number and type of wirebond tiers to be used on the PCB/package
        • Use Tier Properties dialog box and define the tier parameters.
        • Rings are generally used for Power and Ground.
        • Placement guides are used for signals.
        AsPacker Wire Bond Explorer

      • Each tier has it’s own definition and DRC rules.
        • All units are in microns except for Wire Width which can either be Mils or Microns.
        • Only those tiers that are used need to be enabled.
        • Max Length and Max. Angle are used for post process DRC checks.
        Tiers

      • Once the Tiers are defined you add the Die Attach Pad.
        • Use the Die Attach dialog box and define the attach pad.
        • The attach pad can be tailored to your specific needs.
        • The inner ring (ground) can optionally be attached to the die.
        AsPacker Wire Bond Explorer
        Typical Design Flow (3b)
      The Die Attach Pad consists of 3 parts
      • Die Attach Style, where the die is placed, can be either hatched, solid, or none.
      • Die Attach Margin can be set to the size of the die or over / under sized as needed.
      • Inner Ring Attach Points are the connections to the first tier (ring) from the die attach pad.
      Die Attach Pad

        Typical Design Flow (4a)
      Now you are ready to assign pads to tiers
      • Use the Tier Assignment dialog box to assign SBPs (Substrate Bond Pads) to the desired tier.
      • Generally Ground is the inner tier (ring) with Power being the next.
      AsPacker Wire Bond Explorer

        Typical Design Flow (4b)
      Assign pads to tiers.
      • SBPs can be assigned using the pin name, Package pin name or Net name.
      • In the case of signals, you have the option to select multiple pads and split them between specified tiers.
      Tier Assignment

        Typical Design Flow (5a)
      Generating the Fan-Out.
      • Once all the parameters have been set and DRC rules defined in the Tiers dialog box, it is time to generate SBP the fan-out.
      • This is done by using the Fanout Tool.
      AsPacker Wire Bond Explorer

       Typical Design Flow (5b)
      Execute Fanout.
      • There are multiple options that control the fan-out process.
      • You have the option to work on one edge at time or all edges.
      • You can also select a group of pads and work on only those if desired.
      • A log is kept as the process runs for review.
      Fanout

       Typical Design Flow (6)
      The final step is to Export the design.
      • This is done by using the Export LIQ short format menu option.
      • Select the features you want to export and click Export.
      • This produces an LIQ file that can be read into EDWin.
      Export LIQ short

      Advanced Feature – Stacked Die

      Stacked die example
      • U2 is placed on U1 by loading the DemoStacked-Die.pinlist
      • Assign U1 Grounds to tier 1, U1 Powers to tier 2, U1 Signals to tier 3, and U2 all pads to tier 4.
      AsPacker Wire Bond Explorer

      • Select all pads on Tiers 1, 2, and 3 using the Select Tool.
      • Uncheck Keep Pin Order in the Fanout Tool.
      • Execute fanout on selected tiers.
      AsPacker Wire Bond Explorer
      • Unselect tiers 1, 2, and 3 (right mouse click).
      • Select tier 4 with the Select Tool.
      • Execute fanout on the selected tier.


      • The resulting fanout for a Stacked Die is completed and DRC clean.
      • Wires are allowed to cross because tier 4 is dedicated to U2 signals only and bonded last.
      AsPacker Wire Bond Explorer

       Advanced Feature – Split
      Split CBP Example
      • CBPs can be split into 2 or more segments to accommodate multiple bond wires (Powers and Grounds).
      • Use the Split CBP Manager.
      • Select the CBP to be split.
      • Click Split to create segments.
      • Click Join to rejoin segments.
      Split CBP Manager
      • Execute fanout.
      • One segment in this case is 10 and the other is 10.1.
      • Select one of the wires (Shift – mouse swipe).
      AsPacker Wire Bond Explorer

      • Using the Pads Properties dialog box, adjust the CBP wire X and Y offsets.
      • Do the same for the other CBP segment.
      AsPacker Wire Bond Explorer


       Advanced Feature – Stitch
      • You can connect CBPs on one die to CBPs on another die by using stitches.
      • This is a manual process using the Stitch Manager tool.
      AsPacker Wire Bond Explorer
      • You create a Stitch by selecting pads from the 2 drop down lists.
      • Stitches can be added, edited, or removed.
      • You can also save and load a stitch list.
      Stitch Manager

       Advanced Feature – Script

        • As mentioned before, all commands are recorded as they are executed and recorded in a time stamped .log.These logs files can be edited for reuse at a future date as a script .kmd.
        • This is handy for setting up a project or project parameters.
        • Scripts are normally have the extension .kmd while the log file extension is .log.These scripts can be nested to any depth.
        • A script can be executed at the command line by entering “run=“ and script name.
        • A script can optionally be executed with the toolbar Run option.
        • Long running scripts or scripts with wait states can be paused with the toolbar Pause option.
        • Once paused you can step through the script using the toolbar Step option.
        • To terminate a script, press Escape or the toolbar Stop option.

          Options

          There are several project options that allow you to visualize the project in different was as well as how the tool reacts.
            • Fill CBP Pad:Enables viewing the CBPs with filled color or just outline.
            • Display Pad Text: Displays or hides the CBP and SBP pad text.
            • Display Die Attach Pad: Displays or hides the die attach pad and ring connections.
            • Display All Tool Tips: Displays of hides the tool tips for controls.
            • Display Die Only: Displays only the die if selected.
            • Die Origin Center: If selected the coordinate origin is at the center of the die (default) else it is at the Lower Left Corner of the die.
            • Reverse Mouse Wheel Zoom Direction: Reversed how the zoom is done when the mouse wheel is used ot zoom in and out.
            • Cancel Current Operation: Terminates the current operation and deselects all objects.

              Navigation

              There are several ways of navigating around the die.
              • The navigation tool by clicking on one of the 9 buttons to move up, down, right, left, in, out, window view, pan, or view all.
              • By clicking anywhere in the world view to make that point the center of the view window.
              • Using the keyboard by holding the CTRL key down while pressing the arrow keys, PgUp, PgDn, and Home to move around the view window.

              Selecting Objects

              • Objects can be selected by either using the Select Tool or by holding down the Shift or CTRL key while clicking on a start point followed by an end point.
              • Objects within this window are selected.
              • Once an object is selected you can only select other object of the same type.
              • To select wires you do the same operation except you swipe across the wires.
              • A right mouse click or pressing ESC will deselect all objects.

              Basic Editing

              • When objects are selected you have a limited number of editing features.
              • Move allows you to move selected CBPs or SBPs.
              • Move to Tier allows you to move selected SBPs to another tier.
              • Delete will delete selected objects. If a wire is selected the wire and associated SBP are deleted.
              • These editing features are enabled and disabled based on the objects selected.

              Other Tools

              • The Ruler is used to measure point to point distances from one point to another by clicking to start and end. As the mouse moves the X and Y deltas and distance are displayed at the bottom of the screen.
              • The Mouse Wheel is used to zoom in and out. When zooming in the point of the mouse is centered on the screen then zoomed in at that point.
              • The Middle Mouse Button executes a pan.

              Terminology

              • CBP: Component Bond Pad.
              • SBP: Substrate Bond Pad.
              • Wire Bonds: Wires that connect CBPs and SBPs.
              • Die Attach Pad: The place where the die is placed.
              • Rings: Copper rings around the Die normally used for Power and Ground.
              • Stitch: CBP to CBP connections.

              Terminology