Tuesday, 24 April 2012

It compiles the source file and generates wirelist (*.wrs) output file.
The output file (*.wrs) may be imported directly into EDWinXP.
Generates simulatable models in Mixed Mode & EDSpice Model Generators.
Converts the (*.wrs) file to Xilinx,CUPL and JEDEC formats.
VHDL Editor working is very uch similar to any normal programming editor. On compiling the error messages will displayed at the output window below. On double clicking the error the corresponding line in the editor window will get highlighted in Red. This helps in faster debugging of source file.

No comments:

Post a Comment